module xmj_Fractional_Frequency (
	input wire CLK1,
	output wire CLK2
);
	parameter FRAC = 10;
	parameter WIDTH = 4;
	reg[WIDTH - 1 : 0] i;
	initial begin
		i = 0;
	end
	always @(posedge CLK1) begin
		i <= (i + 1) % FRAC;
	end
	assign CLK2 = (i == 0);
endmodule
